1. Field of the Invention
The present invention relates to a PLL frequency synthesizer circuit and to a frequency tuning method thereof.
2. Description of the Related Art
New features are added to miniature mobile wireless devices such as mobile telephones with the advent of each new model thereof, and certain limits are imposed on the external dimensions of the apparatus, and on the weight and price thereof. Therefore, miniaturization/weight reduction/cost reduction is desired for the components used in these devices.
A circuit referred to as a PLL frequency synthesizer for reference signal generation is usually used for sending and receiving a signal in the wireless unit of a mobile wireless device.
A PLL frequency synthesizer circuit is a circuit provided with functionality for the automatic modulation of an oscillation frequency, and the signal that is output by the PLL frequency synthesizer circuit after automatic modulation is used as the reference signal.
It has been quite common in the past for a PLL frequency synthesizer to be composed of an IC obtained by integrating a voltage controlled oscillator circuit (VCO: Voltage Controlled Oscillator) in which a circuit is modularized in a discrete component, a low-pass filter circuit (LPF circuit: Low Pass Filter) composed of discrete components, and other circuits.
In order to reduce the mounting surface area of a PLL frequency synthesizer on the substrate of a wireless unit, frequent attempts have been made in recent years to mount on a semiconductor integrated circuit a voltage controlled oscillator circuit and low-pass filter circuit, which are difficult to mount inside an IC by conventional techniques.
The conventional PLL frequency synthesizer circuit will be described in further detail below.
<Description of the Basic Structure and Operation of a PLL Frequency Synthesizer>
FIG. 9 is a block diagram showing the structure of a common PLL frequency synthesizer circuit.
The PLL frequency synthesizer circuit depicted in FIG. 9 is composed of a feedback loop made up of the phase comparison circuit 901, the low-pass filter (LPF) circuit 902, the voltage controlled oscillator circuit 903, and the divider circuit 904. The oscillation output 908 thereof is used as the reference signal of the transmitter circuit and the receiver circuit of the wireless communication circuit.
The phase comparison circuit 901 detects the phase difference between the reference signal 905 output by the PLL frequency synthesizer and the output 909 of the divider circuit 904, and outputs a current or voltage 906 that is proportional to this phase difference.
The low-pass filter circuit 902 supplies the voltage controlled oscillator circuit 903 with a signal 907 obtained by removing the high-frequency component from the output 906 of the phase comparison circuit 901.
The divider circuit 904 feeds back to the phase comparison circuit 901 a signal 909 obtained by substituting the frequency of the output 908 of the voltage controlled oscillator circuit 903 into the expression 1/N (N division).
In this type of PLL frequency synthesizer circuit, the phase of the signal 909 is modulated so that the output 906 of the phase comparison circuit 901 is zero.
The frequency of the oscillation output 908 in a steady state thereby becomes the Nth multiple of the frequency of the reference signal 905.
<Description of the Structure and Operation of a CMOS VCO (Voltage Controlled Oscillator Circuit)>
It was mentioned above that in order to reduce the mounting surface area of a PLL frequency synthesizer on the substrate of a wireless unit, frequent attempts have been made in recent years to mount on a semiconductor integrated circuit a voltage controlled oscillator circuit and low-pass filter circuit, which are difficult to mount inside an IC by conventional techniques.
FIGS. 10 through 12 are circuit diagrams showing the voltage controlled oscillator circuit composed of CMOS transistors described by Abidi et al. of UCLA in “A Filtering Technique to Lower Oscillator Phase Noise,” Analog Techniques Lecture No. 4, ISSCC (International Solid-state Circuits Conference) 2001, Session 23.
FIG. 10 shows the base circuit thereof.
The base circuit shown in FIG. 10 is provided with the first and second inductors 1001 and 1002, the first and second variable capacitor elements 1003 and 1004, and the first through third NMOS transistors 1005, 1006, and 1007.
In the circuit shown in FIG. 10, NMOS transistors 1005 and 1006 are used as active elements for obtaining negative resistance, and a MOS capacitor that uses the space between a gate and a back gate made up of the NMOS transistors 1003 and 1004 is used as a variable capacitor element. The capacitance values of the NMOS transistors 1003 and 1004 are equivalent to each other, and the inductor values of the inductors 1001 and 1002 are equivalent to each other.
In the oscillator circuit of FIG. 10, if Cv is the capacity of the NMOS transistor 1003 or the NMOS transistor 1004, and L1 is the inductor value of the first inductor 1001 or the second inductor 1002, then the parallel frequency of Cv and L becomes the oscillation frequency fvco1, which is found from equation (1).fvco1=1/(2·π·(L1·Cv)1/2)  Equation (1)
In FIG. 11, in order to widen the oscillation frequency range, the base circuit in FIG. 10 is provided with capacitor switching circuits (Tuning Capacitor circuits) 1011 and 1012 provided with variable capacitor elements corresponding to the NMOS transistors 1003 and 1004.
In FIG. 11, the capacitor switching circuits 1011 and 1012 are each configured as shown in FIG. 12, and the variable capacitor element 1021 corresponds to the NMOS transistor 1003 or 1004 in FIG. 10. The capacitor switching circuits 1011 and 1012 are provided with a variable capacitor element 1021; capacitors 1022, 1023, and 1024 whose capacitance values are weighted C, 2C, and 4C, respectively; and NMOS transistors 1025, 1026, and 1027. The parallel capacity Cvp composed of the variable capacitor element 1021 and the capacitors 1022, 1023, and 1024 can be varied in a wide range by controlling whether the capacitors 1022, 1023, and 1024 are grounded or not grounded (GND) according to the “on” or “off” state of the NMOS transistors 1025, 1026, and 1027. By varying the control voltage Vc applied to the back gate of the variable capacitor element 1021, the parallel capacity Cvp composed of the variable capacitor element 1021 and the capacitors 1022, 1023, and 1024 can be finely adjusted. If the relationship between the range ΔCvp of the Vc-induced capacity variation of the variable capacitor element 1021 and the capacitance value C of the capacitor 1022 is set such that C<ΔCvp, then the resonance frequency of the inductor 1001 and the capacitor switching circuit 1011, and the resonance frequency of the inductor 1002 and the capacitor switching circuit 1012 can vary continuously, and the oscillation frequency fvco2 can also vary continuously. It therefore becomes possible for fvco2 to vary in a wider frequency range than the circuit in FIG. 10, and if L2 is the inductor value of the inductors 1001 and 1002, then fvco2 is found according to equation (2).fvco2=1/(2·π·(L2·Cvp)1/2)  Equation (2)
In Japanese Unexamined Patent Application Publication No. 2001-352218, an example of a configuration in which the capacitor switching circuit in FIG. 13 is configured using only a variable capacitor element is described as a mechanism for varying the oscillation frequency of a CMOS VCO in a wide range.
Specifically, as shown in FIG. 13, the circuit in this example is provided with a plurality of variable capacitor elements 1111, 1112, 1113, and 1114; frequency control terminals 1121, 1122, 1123, and 1124 that correspond on a one-to-one basis to the variable capacitor elements 1111 through 1114, respectively; a resonance circuit 1101; a negative resistance circuit 1102; and a transmission output terminal 1103. A function equivalent to that of the capacitor switching circuit in the circuit of FIG. 11 can be performed by switching the bias potential applied to the frequency control terminals 1121 through 1124 to the maximum potential and minimum potential at which the capacity variation of each of the variable capacitor elements 1111 through 1114 corresponding thereto is saturated.
However, in a PLL frequency synthesizer circuit that uses a VCO whereby the frequency can vary in a wide range by the switching of capacitors in the type of capacitor resonance circuit shown in FIGS. 10 through 13, a mechanism must be provided for retrieving the set value of the switched capacitor in advance so that the frequency for which locking in the range of the VCO oscillation frequency is desired exists prior to the frequency lock operation of the PLL loop.
The VCO circuit shown in FIG. 13 also uses an N-Well capacitor, which is a type of MOS capacitor, in the variable capacitor element for adjusting the oscillation frequency of the VCO. A detailed description of the method for correcting fluctuations in the characteristics of the N-Well capacitor is found in paragraph Nos. 23 and 24, FIGS. 3, 4, and 5, and elsewhere in this related patent application.
Specifically, the following description is given in paragraph No. 23 of the related patent application: “For example, a constant voltage determined in advance is applied from the frequency control terminal 8 during the factory shipping inspection, and unevenness in the frequency due to fluctuations in manufacturing can be corrected.” However, in a method for applying a constant voltage to the control terminal, situations can be envisioned in which this constant voltage becomes equal to the electrical potential at which the capacity variation characteristics of the N-Well capacitor are saturated due element variance, and this method may not be considered suitable for large-scale production.
Paragraph No. 24 of the related patent application also describes an example of a method whereby the frequency is monitored by a counter or the like, and the result thereof is fed back to the control voltage output by the frequency correction signal generating circuit, but when the characteristic variance of the N-Well capacitor is large, it is highly likely that errors (unevenness) in the oscillation frequency could exceed the range of correction obtained merely by adjusting the potential applied to a single N-Well capacitor.
The present invention was developed in order to overcome such drawbacks as those described above, and an object of the present invention is to provide a PLL frequency synthesizer circuit and a frequency tuning method thereof whereby the oscillation frequency of a voltage controlled oscillator circuit can be caused to approach a desired lock frequency more reliably than by the conventional technique.